1. Field of the Invention
The present invention relates to a semiconductor device which is manufactured by monolithically integrating a Power MOS FET, that is a power insulated-gate type FET having a drain region of high resistance, and a small-signal semiconductor or control transistor element in a single semiconductor substrate in which the small-signal semiconductor element is employed for controlling the Power MOS FET.
2. Description of the related art including information disclosed under 1.97-1.99
An explanation will be given below of one conventional form of a composite semiconductor device manufactured by monolithically integrating in a single semiconductor substrate a Power MOS FET having a drain region of high resistance, NPN transistor; and MOS transistor. FIG. 1 is a cross-sectional view showing a semiconductor device. A Power MOS FET will be explained below by way of example. The semiconductor device as shown in FIG. 1 includes N.sup.+ drain regions 1, 2 having a low resistance, an N.sup.- type drain area 3 having a high resistance, a P type body 4, an N.sup.+ type source region 5 and a gate electrode 6. An NPN transistor will be explained below in connection with the semiconductor device shown in FIG. 1. The semiconductor device further includes an N.sup.+ type collector region 7 having a low resistance, an N.sup.- type collector area 8a having a high resistance, a P type base 9, an N.sup.+ type emitter 10 and an N.sup.+ type collector region 11 from which a collector current is taken out for external connection.
A CMOS transistor will now be given below in connection with the semiconductor device shown in FIG. 1. The semiconductor device further includes a CMOS transistor having an N.sup.- type area 8b, a P.sup.- type well 12, an N.sup.+ type drain region 13a and an N.sup.+ type source region 13b of an N channel MOS FET within P.sup.- type well 12, gate a electrode 15 of an N-channel type MOS FET, P.sup.+ type drain region 14a and P.sup.+ type source region 14b of an FET and gate electrode 16 of a P channel MOS FET. P.sup.+ type regions 17a and P.sup.+ type region 17b provide an electrical isolation, by PN junction isolation method, among the Power MOS FET, NPN transistor and C-MOS transistor.
According to the conventional technique, drain area 3 having a high resistance in the Power MOS FET, N.sup.- collector area 8a having a high resistance in the NPN transistor and area 8b in the CMOS FET transistor are simultaneously formed in the semiconductor substrate by an epitaxial growth method. In this way, these regions have the same resistivity, but an optimum resistivity normally differs among the drain region of high resistance in the Power MOS FET, high resistance region in the NPN transistor, and so on. An optimum resistivity value of the drain region having a high resistance in the power MOS FET should be about 1 .OMEGA..multidot.cm, for instance, at V.sub.DSS =60 V where V.sub.DSS represents a maximum drain-to-source voltage at the time of short-circuiting betweem the gate and source circuits of an associated transistor. On the other hand, an optimum resistivity value of the collector region having a high resistance in the NPN transistor should be about 6 .OMEGA..multidot.cm, for instance at V.sub.CEO =60 V where V.sub.CEO represents a maximum voltage between the collector and the emitter of an associated transistor with a base open-circuited. If the Power MOS FET and NPN transistor are integrated, as a Power-IC, in a single semiconductor substrate, when areas 3 and 8a are so formed as to have a resistivity value fitted for the NPN transistor, then the drain-to-source voltage V.sub.DSS of the power MOS FET becomes greater than necessary with the result that the ON resistance per unit area becomes much greater. Thus the area of the power MOS FET necessary to obtain a desired ON resistance becomes much greater when the power MOS FET and NPN transistor are integrated in a single semiconductor substrate than when the power MOS FET is formed as a discrete part, resulting in a poor yield. Where areas 3 and 8a are formed with a resistivity value suitable for the Power MOS FET, restriction is imposed on the collector-to-emitter voltage V.sub.CED of the NPN transistor, making it very difficult to achieve a circuit design involved.
If the control transistor element and the Power MOS FET having a drain region of high resistance are to be monolithically formed on a single semiconductor substrate, they are usually formed simultaneously, for example, by an epitaxial growth so that they have the same resistivity value. This resistivity value is properly selected in view of the characteristics of both the the control transistor element and the power MOS FET. In the conventional techniques it is very difficult to make the characteristics of the Power MOS FET within the aforementioned composite semiconductor device, such as the ON resistance and withstand voltage, equal to those of the Power MOS FET manufactured as a discrete element.
The application of this type of composite semiconductor devices has been quickly expanding and the demand for a wider characteristics window for each element integrated in the device has been increasing. Therefore is very important to optimize the design of the device as if each element integrated therein is mutually independent like a descrete element.